In designing high performance integrated circuits, the high speed transfer of addresses and data between circuit blocks is a critical consideration. This is especially true in applications where a memory and a high performance state machine are being integrated into a single chip. One such instance is when a display controller and a frame buffer are being integrated to produce single-chip high performance display control device. In this case, substantial amounts of data, and the corresponding addresses, must be transferred between the graphics controller and the frame buffer at rates high enough to support display refresh and update, and other processing operations such as filtering. As display systems with increased resolution and bit depths are developed, the rate at which data must be transferred between the controller and the frame buffer consequently increases. While some of the necessary bandwidth can be achieved by using wide buses, improvement in the speed at which data is transferred over the individual bus lines is still required.
The lines of a typical on-chip bus are long, thin conductors which extend relatively substantial lengths across the face of the substrate, the substrate spacing each conductor from the chip ground plane. As a result of this configuration, each line presents a significant capacitance which must be charged or discharged by a driver or similar circuit during data transmission. The result is substantial power consumption, in particular when the driver is driving one or more bus lines towards the positive voltage supply rail to transmit logic high data. This power consumption is primarily due to bus line capacitance, which increases directly with the data transmission rate across the bus conductors. In general, P=CV.sup.2 f, where P is the power loss through each conductor, V is the voltage applied, C is the capacitance of the conductor and f is the frequency at which the conductor is charged/discharged. It should also be noted that some additional power consumption results from the resistance of each bus line.
It is possible to reduce power consumption by reducing the capacitance of the bus lines themselves. This option however requires that the fabrication process for the chip be modified. Such a change in process to reduce line capacitance would be expensive and may adversely effect the fabrication of other circuitry on the chip, Another option is to reduce the frequency at which data is transferred across the bus. Assuming that the width of the bus is not increased, this option simply trades off system performance for power reduction, an option which usually is not viable in the design implementation of high performance devices.
Thus, the need has arisen for improved circuits, systems and methods for the high speed transfer of data and/or addresses across the lines of a bus. Such circuits, systems and methods should advantageously minimize power consumption and the problems attendant therewith. In particular, such circuits, systems and methods should be applicable to high performance integrated circuit applications, such as when a display controller and frame buffer are integrated on a single chip. Finally, such circuits, systems and methods should neither require expensive and complicated changes to the chip fabrication process nor require a reduction in system performance for implementation.